3D Packaging — August 2011
Change Language:
Company Insight

“Tong Hsing’s strategy is to pursue niche markets with high barriers to entry,” Says Heinz Ru, TheIL.

Carving out a ‘niche’ in custom microelectronics packaging

Tong Hsing electronic Industries Ltd. Knows a little something about the custom microelectronics manufacturing business. In fact, it’s spent the past 35 years amassing a wide array of IP building blocks, which the Taiwan-based company leverages to tailor special “recipes” for the widely varied and specific needs of its customers.

Tong Hsing is known primarily for its contract manufacturing of microelectronic packaging and fabrication of thick- and thin-film ceramic substrates. However, Tong Hsing has a wide range of other special technology solutions and capabilities that include module substrates for LeDs, RF modules for cellphones, system-inpackage (SiP) technologies, unique packaging solutions for MeMS and CMOS image sensor devices, reconstructed semiconductor wafers, chip probing and final test, PCB assembly, automotive hybrids, thin film on alumina and aluminum nitride (AlN), and thick film on alumina.

Tong Hsing’s strategy is to pursue niche markets with high barriers to entry, markets where they can create a unique solution, “custom fitting the shoe to the customer,” so to speak. Working with startups is a key part of their business strategy. While far and away the majority of these startups fails (80 to 90%), as is unfortunately common in the niche areas, the investment in the 10 to 20% that succeed has enabled the company to grow along with them.

Heinz Ru, vice president of Marketing and Innovation says: “Our strategy is to avoid very mature or commoditized technologies. For commercial projects there’s always a narrow time window for implementation—6 to 18 months. But if you’re a startup trying to put all the pieces together in this timeframe, you have no chance. We’ve been gathering the core technology building blocks, have the experience and reliability data, and have already learned the difficult lessons. Tong Hsing knows its ‘building blocks’ inside and out and can reorganize and reassemble them quickly—greatly increasing the odds of our startup partners being among that 10 to 20%.”

The company doesn’t work exclusively with startups, it also works with industry giants such as Texas Instruments, Delphi, national Semiconductor, Skyworks, and many more.

Headquartered in Taipei, Taiwan, Tong Hsing has manufacturing facilities located both in Taiwan and the Philippines. Ru is quick to point out that having a very capable, stable workforce such as theirs helps ensure quality. And the company’s resources Are always prepared in advance; for example, 20% more capacity is always available just in case it’s needed.

Off the roadmap trends

As the company is involved in many “off the roadmap” technologies, Tong Hsing offers a unique perspective on emerging trends and areas of future growth.

CERAMICS REVIVAL

One of the most interesting trends Tong Hsing is witnessing now is a ceramics revival. “Ceramic substrates used to be a big industry for us, but it shrank rapidly after the 1990s,” says Ru. “Surprisingly, we’re seeing many industries beginning to switch over from mainstream technologies to ceramics. For example, LeDs are now using ceramic substrates as a Level 1 packaging solution to interface with the chip. About 8 years ago we thought our ceramic business was dying, but now all kinds of new applications are popping up. Another example is solid oxide fuel cells, where the heart of the cell operates at 800° to 850°C to reach the desired efficiency. What material can reduce that temperature? Ceramic. It’s extremely fortunate for us that we didn’t decide to shut down that business.”

LEDS

Among the trends emerging in the LeD area are: a shrinking substrate size; a shift in high growth market segments experiencing growth; a shift from lower thermal performance alumina substrates to higher thermal performance aluminum nitride substrates; and strong market pressure to reduce cost, similar to what happened in PA modules for handsets.

These PA modules that used to be 10x10 mm are shrinking down to 6x6, 4x4, and 3x3 mm, so the substrates are shrinking as well. The LeD substrates are taking the same path to shrink the size to reduce the cost, explains Ru.

He’s also seeing the back light market flattening out. “Growth, especially for LeD Tv segments has slowed quite a bit,” he adds. “even though the penetration rate is greater, because of the efficiency and other material improvements, fewer units are being used in each LeD Tv. The next area of growth we’re expecting is for general lighting, and for this growth we need to drive more power into the die and chip.”

Thermal performance also needs to improve, so there’s a fast-paced trend of moving from alumina substrates to aluminum nitride substrates. Last year, a mere 1% of Tong Hsing’s substrate sales were for aluminum nitride, while 99% were for alumina. Now, they’re seeing a big change: 20% Aluminum nitride, 80% alumina. Ru expects this is a trend that will continue.

Another trend is that customers are looking for ways to reduce LeD costs quickly, because the current pricing of LED light fixtures is too expensive. Even with the shift to aluminum nitride substrates, the cost remains prohibitively high. “Aside from the LeD area, the aluminum nitride industry was built on high-power, high-frequency communication applications, as well as laser diodes,” says Ru. “neither of these require many aluminum nitride substrates, so they can afford the high cost— based on the volume they use. But for LeDs it’s different. Today, the standard thermal conductivity of aluminum nitride is 170, while alumina is only 20. Our customers are telling us that they need conductivity in the range of 120 to 140. They can only afford a solution that costs much less than they’re currently paying now. We believe that with this volume increasing, someone will come up with a good solution.”

MEMS

As for MeMS trends, stress is still a big issue for certain applications, so ceramics are used in pressure sensors. Many MeMS devices are used in automotive applications, which are highly corrosive environments, so ceramic is preferred for that too.

CAMERA MODULES

In camera modules, to shrink the thickness, flip chip is the solution. Many of the high-resolution smartphone camera modules are using goldto- gold interconnects (GGI) and ceramics. “The reason for this is that the GGI puts high pressure on the substrate at a high temperature. PCBs Become soft at high temperatures and aren’t reliable, so they’re going back to the reliable ceramics,” explains Ru.

PACKAGING TRENDS

One interesting packaging trend Tong Hsing is watching emerge is how the business models are changing in the off-the-roadmap packaging market. “It’s still largely a question of who’s going to play? Who’s going to win marketshare? Which technologies will prevail?” points out Ru. For now, he says it’s difficult to guess and that having a flexible mindset is necessary since nothing is set in stone yet. “We work closely with the product, and discover who owns the IP, who understands the market, and who has the best connections with end-customers—we essentially figure out who can help put us in the driver’s seat. In offering custom-made services, we share some of the profits.”

Ru believes that basically, if you’re a packaging house just focusing on a narrow segment of the process, for example, such as focusing on die attach wire bond or plastic bonding, you can certainly survive, but the future won’t be as bright. “To really thrive, it is critical to look at emerging requirements,” he adds. “We see potential in LeDs and concentrated photovoltaic, which we expect to grow. We also expect power modules for motor drives or inverters to grow.”

Growth ahead

Tong Hsing is viewing a rapid increase in activity going on in power electronics right now, so the company plans to direct more resources into that area. The company is also interested in fuel cells, as well as biomedical devices, and is actively working on related projects in these areas. “These are relatively new technologies,” Ru notes. “The markets are still quite small and it may take several years to evolve, but we’re willing to make the investment now.”

Among Tong Hsing’s top goals for this year are: becoming the leading foundry service provider of RF modules, SiP, and MeMS packaging in Asia Pacific; continued expansion of the production scale of thin-film DPC substrates used in HB LEDs, solar cells, and electric vehicles; a ramp-up in production of ultraHB LeDs used in projectors; an expansion into the commercial aircraft industry; an expansion into fuel cells; a ramp-up of medical electronic circuit production; and a continued expansion in the production scale of image sensors, which includes chip probing, wafer reconstruction, assembly and final test.

As Tong Hsing has discovered, finding and embracing these off-theroadmap niches can really pay off.

www.theil.com

Heinz Ru, Vice President, Tong Hsing Electronic Industries

He has been with the company for more than 30 years. He started in 1976 and an engineer and has worked in engineering, operations, sales, marketing, and new business development. Ru holds an MBA degree from national Chiao Tung University, and a bachelors degree in electrical engineering from national Taiwan University.

“The first market segment requiring BSI technology in volume is obviously the mobile phone” says Julien venturini.

“The first market segment requiring BSI technology in volume is obviously the mobile phone” says Julien venturini.

Excico ultra-fast laser annealing solutions reach thermal constraint specifications for BSI and 3DIC

Increasing complexity of 3D stacks as well as BSI CMOS Image Sensors has haled equipment manufacturers to develop new solutions to provide fast annealing without degrading active layers and interconnects. In this new issue, Julien Venturini, Marketing Director of Excico, presents the benefits of Laser Thermal Annealing (LTA) especially for BSI application and shares his feelings about drivers and motivations for this emerging technology in semiconductor wafer processing.

Yole Développement: Could you present to our readers the activity and products of Excico ?

Julien Venturini: excico is a european company supplying annealing equipment to the semiconductor and photovoltaic industry. Today organized globally with support with a worldwide footprint, our company supplies the semiconductor industry with the most scalable annealing technologies and solutions. The company activity and mission is to fulfill a gap in the ultrafast annealing solutions required in present and future process flows of semiconductor foundry and IDM’s.

The value of our Laser Thermal Annealing (LTA) platform and process solutions is the capability to improve thin layers implemented in semiconductor fabs at the nanometer scale without affecting buried functional layers and with a very homogeneous process across the whole device area.

This improves and locks-in the electrical surface properties of a semiconductor with an ultra-low thermal budget with no damage of the device underneath. A historic step in the “diffusion” vendor’s industry was achieved few years ago when excico installed production equipment for thin Wafers backside annealing. This was the first time that a semiconductor fab was processing wafers with a melt-mediated annealing process. We enabled a process where one renders a very thin layer of silicon at the liquid state and recrystallize this layer over few tens to hundreds of nanometers (>1400°C) while remaining at room temperature (20°C) at the other side of the wafer. Excico provided this industrial process solution first to Power Devices Fabs but has today extended its application portfolio to CMOS Image Sensors and is also developing solutions for Memories, Processors, LeD and Solar Cells Markets.

Yole Développement: According to you, what are the main key features and advantages of BSI sensors compared to standard FSI CMOS image sensors ? How do you explain the different motivations for BSI technology to enter the high-end video camera imaging versus the low-end consumer / mobile type of CMOS imaging applications

Julien Venturini: The key advantage of Backside Illuminated CMOS imaging sensors technology is a Fill Factor in each pixel of 100%, while this is impossible to achieve with the front side illumination device where transistors are shading the incoming light to be detected. Therefore the sensitivity is improved allowing manufacturers to reduce pixel size without damaging the device performance.

There were several niche developments and productions of BSI sensors the last years, mainly for low volume high end scientific, military and aerospace applications. But the first market segment requiring BSI technology in volume is obviously the mobile phone where the market is still driven by a strong pixel number appeal while requiring a small embedded imaging sensor. But adoption of the technology in mass production is only possible if one can master the process on 200 and 300 mm wafers. There are other reasons for BSI adoption in still imaging device like DSLR camera and one of them is the large acceptance angle range of the pixel which is an interesting asset when it is required to change the imaging lens of the camera.

The sensitivity increase can also be used for the exposure duration reduction at constant pixel size. This comes to your second question where there is a clear application of this feature for video camera. This is even more useful in the case of high resolution applications.

There were technology roadblocks preventing rolling out the BSI technology for consumer applications at a relevant cost, but they are today mastered by most of our customers. In a nutshell we can say that the BSI CIS technology can theoretically be used on most of the imaging application. A strong driver of BSI adoption is also the use of 3D stacking and Tsv processes. The additional cost of BSI processes can be compensated by increasing the number of die per wafer by using Tsv technologies, and stacking vertically functionalities that were originally occupying areas aside the sensor itself on the die.

Yole Développement: In our last Power Dev’ magazine, you presented the needs for backside laser annealing in power devices manufacturing. Could you tell us more about the use of this technique for BSI type of CMOS image sensors?

Julien Venturini: You are right that the concept of the process is very close to the one of backside annealing of IGBTs. The goal is to anneal the flat backside surface of the device while not damaging the buried front side. The main difference between the two applications is that the device thickness is only a couple of ìm in BSI while it is 40 to 100 ìm for IGBTs. The thermal constraint of BSI CIS means that the temperature has to be below 400°C at 2 to 5 ìm under the top surface (actually backside) of the device not to damage metallic lines of the front side Process. The other difference is in the very strong sensitivity of the device to defects and to dopant profile. We went through several adjustments of the process parameters with our partners to optimize the device performances. The process integration has been facilitated by some thermal simulations which are also a knowhow that excico provides today.

The role of the Laser annealing is to improve the backside passivation by forming a shallow electrical junction and there are many ways to optimize that. The challenge is to keep the blue sensitivity of the device and to void any other recombination center formation.

Yole Développement: Could you comment on the intrinsic advantages of Excico’s excimer laser tool versus the more common Green YAG laser tools available on the market?

Julien Venturini: excico platform is today supported by a very specific Excimer laser technology which delivers a very large area (several cm²) which covers one or several devices in a single shot, while 308 nm enables a very thin absorption depth.

That is why the 532 nm wavelength of YAG lasers cannot be easily implemented in a tight vertical control (few tens of nanometer junctions) of a semiconductor annealing process. The main bottleneck is that the wavelength is absorbed deeper in the semiconductor. The other issue is the small energy of the laser which requires having stitching areas between two consecutive pulses across the device. Consequences are 3 fold: 1- It induces more heat at the other side of the wafer and 2- the process variability and the control of the junction thickness are four times higher due to a slower gradient of heat Close to the targeted temperature window, 3- the performance and uniformity of the device is not matching the market expectations.

We don’t see today the green laser to be able to reach high added value processes like those required in BSI CIS or in other mainstream Semiconductor market like LOGIC or Memories. Nevertheless there are probably other applications, when the thermal budget is not a constraint, where this laser technology can also be implemented. Although we own a very specific Excimer technology, Excico is not a ‘single laser technology’ company. As an annealing equipment vendor, and given our extended expertise in laser semiconductor interactions and processes, we are very carefully looking at other laser technology that could be integrated in an excico existing platform provided it can serve our customer needs and roadmaps.

Yole Développement: Who are the leading players of the BSI imaging landscape (IDM’s versus foundries)? What it the status of 200mm versus 300mm in the today’s BSI landscape?

Julien Venturini: 300mm wafer capability appears to be a critical asset to penetrate the mobile phone market. But 200mm fabs have in front of them a couple of very attractive BSI market segment as well, including DSC and video Cameras which account for a significant volume (wafers and $) as well. Today both IDMs and foundries are dominating the BSI landscape which is a good thing for the market. As you know different BSI technologies are today implemented in different IDMs and foundry fabs with different process flows and cost models. It provides flexibility to the end customers while allowing a wide span of potential applications and market segments to be further developed.

Yole Développement: Excico laser annealing equipment is also applicable to future “Monolithic 3DIC integration”. Could you comment on the drivers and motivation to use such process in future semiconductor IC processing?

Julien Venturini: Our customer’s technology roadmaps are adding more functionality per unit area to semiconductor devices. This requires more complexity of the device’s design illustrated by what is called the “More than Moore” 3D stacking law. It pushes the introduction of more materials requiring improving their properties through annealing while controlling vertical 3D processing tightly. This approach is mandatory to increase yield or just simply to enable the manufacturing of the device. Low thermal budget provided by LTA combines a high performance and a cost saving approach preserving process integrity along the complete manufacturing cycle.

‘3D More than Moore’ illustrates itself in standard wafer level packaging but also in what is called 3D IC’s where several stack of core devices are homogeneously stacked at the device scale level. This concept is today developed by our customer and the LTA specifications are enabling them to accelerate their roadmap development.

We can identify three main drivers for ultrafast annealing added value in 3D manufacturing approaches:

1. First, the need to reach metastable thermal processes is identified for instance in dopant activation for silicon-based devices, but also in specific defect control processes where the short duration of the heat pulse can selectively cure defects. The melting phase is here key to induce such specific ‘out of equilibrium’ processes that standard processes are unable to reach.

2. Second, LTA tools typically deposit a very low thermal budget which represents in average the equivalent power of a 40 Watt light bulb on the wafer. By balancing the laser process parameters, the LTA equipment enables :

i. negligible thermal stress compared to other classical annealing tools: breakage or yield issues due to wafer warpage after the heat wave are then totally avoided.

ii. Improvement and locking-in the electrical surface properties of a semiconductor without affecting layers and/or devices buried underneath. This is a key asset to all present and future developments of 3D device stacking.

1. Third but not least, the cost and yield of manufacturing. Advanced 3D devices processes are complex and costly when using standard low thermal budget processes available today..

i. The cost per wafer and per move of a low temperature epitaxial layer growth process is several tens of % higher than the LTA’s one

ii. LTA process cancels several manufacturing steps of the process flow by saving forth and back move between Front end of Line and Back end of Line areas. This is valued even more recently with the thin wafer approaches of the 3D Memory markets where yield, breakage rates and number of moves are closely correlated.

iii. The third contribution to cost reduction is the capability to increase the parametric yield over the wafer. The capability to cover a single or several die in a single shot enables a very high reproducibility of the process performance over the whole wafer. The step and repeat LTA process doesn’t shows the temperature gaps between the edge and the center of the wafer reported in standards annealing processes.

The future of the microelectronic lies also in 3D and excico is today an enabling actor.

www.excico.com

Julien Venturini, Marketing Director, Excico

He received his PhD degree from Pierre and Marie Curie University (Paris) in 1999, in the field of Optics and Photonics and was completed lately by a MBA from HeC (Paris). He spent few years in SOPRA Laser Business Unit as Marketing and Application manager where he qualified and developed several Laser based processes for semiconductor and photovoltaics markets. He co-founded excico in 2007 where he is today head of Marketing.

“The two most common types of semiconductor packages used for MEMS cavity packaging are the leadframe based QFN and the laminate substrate based,” says Chris Stai, Unisem.

Cavity packages for volume MEMS applications

MeMS is a dynamic and fast growing market segment that has a broad landscape of packaging needs with not many agreed upon industry standards.

There are many reoccurring requirements that the MeMS manufacturer demands from a high volume cavity package. First the cavity package must protect fragile MeMS features from external forces while still allowing them access to the external atmosphere.

The cavity package is used to de-couple the MeMS die from the thermal and mechanical effects of the second level assembly and the final application.

The solution must be flexible in design and allow System in Package concepts. While having these attributes, the cavity package must be able to meet rigorous reliability standards as per JeDeC and others. And of course the constant challenge for any volume package solution, this all must be accomplished while at the same time be cost effective and competitive.

The two most common types of semiconductor packages used for MeMS cavity packaging are the leadframe based Qfn and the laminate substrate based Ball Grid Array (BGA) / Land Grid Array (LGA). One direction that has begun to take a foothold in the industry’s push for a high volume solution is the use of the LGA style package as the foundation for the MeMS cavity package.

Three LGA based solutions have been introduced to the industry as high volume solutions for MeMS cavity packaging. The basic formats are the LGA Formed Lid Package (LGA-FLP), the LGA Molded Cavity Package (LGA-MCP) and the LGA Molded Lid Package (LGA-MLP). Each has unique attributes that make them strong solutions for specific MeMS devices and applications. The assembly and test infrastructure for LGA based packages is very mature and the processing in strip format provides improved volume throughput and the cost savings associated with high volume processing. The accepted standard material sets are also very mature and are used by many subcontract assembly and test services (SATS) providers in many countries and regions worldwide.

The LGA-formed lid package has a stamped metal lid that may or may not have a pressure port depending on the specific application. Options for this package include multiple die and stacked die designs, standard wire bond or flip chip die bonding.

Other options include the additions of passives and other components used for system-in-package (SIP) solutions.

The LGA-molded cavity package uses a BGA style molding system with a cavity vacuum tool to create a custom package where die can be either molded or placed into a cavity created by the mold and enclosed by a flat metal, plastic or glass lid. For multiple die applications, each die can have a custom environment. Options for the LGA-MCP package are multiple and/or stacked die, wire bond or flip chip, passive components for SIPs, full die coat and top or bottom ports.

The LGA-molded lid package has a custom molded lid that can be more complex than a metal stamped lid. Also unlike the LGA Metal Lid Package, this finished package has square sides. Similar to the other two cavity package solutions, This package can have multiple and/or stacked die, wire bond or flip chip die connection, passives for SIPs, ports on the top and bottom of the package.

The three LGA based cavity packages described can all meet the stringent requirements of the common reliability tests for standard package types.

They pass moisture sensitivity level 2a which is a pre-bake for 24 hours at 125°C, TH at 60/60 for 120 hours and three reflows at 260°C. They pass Temperature Humidity and THB 85/85 for 1000 hours as well as Temperature Cycle from -65 to +150 degrees (500 cycles). The test for High Temp Storage at 150°C is also able to be passed at 1000 hours. However, because of the nature of these types of packages, they are not able to pass Thermal Shock – Liquid to Liquid.

www.unisemgroup.com

Chris Stai is the senior manager of marketing communications and oversees all external communications for Unisem Group. Prior to his appointment with Unisem, Stai held various positions at Advanced Interconnect Technologies (AIT) which was acquired by Unisem in 2007. Stai started at AIT in 1996 as a senior marketing specialist and quickly rose in the ranks to his current position. Prior to AIT, Stai held brand marketing and event management positions with Hi-Tec Sports, a global sporting goods manufacturer.

Stai has a bachelor’s degree in business administration from the California State University, Stanislaus.

“Current probe technology cannot access TSVs or micro-bumps,” says Santa Bansal, Cadence.

3D-IC challenges: design with test (Part 1/2)

With numerous product announcements and technological advancements in the past 12 months, 3D-ICs using through-silicon vias (TSvs) have emerged as a proven, viable technology that offers compelling advantages in power, performance, form factor, and time-to-market.

By making it possible to stack analog, digital, logic, and memory dies at different process nodes, 3D-ICs offer what may be the best alternative to the skyrocketing costs of advanced process nodes.

There are multiple design challenges in 3D-IC Silicon Realization, as noted in a recent whitepaper and Chip Design Magazine article. However, design for test (DFT) is one of the most challenging areas. 3D-IC stacks will be deployed only if they are cost effective, and they will be cost-effective only if they’re testable and offer reasonably good yields.

While wire-bonded systems-in-package (SiPs) may have a few hundred interconnects, 3D-ICs may have thousands if not tens of thousands of interconnects. Even a single defective Tsv can render an entire stack unusable. If individual Tsvs have 99.9% yield, at least one defective Tsv can be expected in a stack with 1,000 Tsvs.

A sound test methodology for 3D-ICs is necessary in order for IC designers to have the confidence to design them. Designers will not start 3D designs without knowing how to make them fully testable. Likewise, test equipment manufacturers and assembly houses cannot plan a production test environment without knowing which failure mechanisms to look for, how to cost-effectively assure known-good die (KGD) prior to stacking, how to thoroughly test stacks during the assembly process, and how to best perform exhaustive final tests.

Some obvious questions around 3D-IC DFT are: Who tests what portion of a 3D stack, and when? Are there new fault types associated with Tsvs and micro-bumps? How can testers access Tsvs and micro-bumps, since they are too small for today’s probe technology? Will transistor behavior change due to the wafer thinning process? How is it possible to control and observe individual dies, even though the only access to test signals is usually on the bottom die in the stack?

Fortunately, solutions are starting to emerge. A number of papers and tutorials at recent conferences and workshops have addressed challenges and potential solutions for 3D-IC test.

Innovation is ongoing both in design for test (DFT) and in tester and probe card technology.

This article provides a general overview of 3D-IC test challenges, and describes a DFT architecture developed at the imec research institute in cooperation with Cadence Design Systems. The architecture enables the modular testing of dies and Tsv-based interconnects by using die-level wrappers that isolate the individual dies from the stack. A subsequent article will focus on needed improvements and technical progress in tester and probe technology.

3D-IC test challenges – Test flows

According to erik Jan Marinissen, principal scientist at imec, 3D-IC test challenges can be understood in terms of test flows (what to test when), test content (what test data is needed for likely defects), and test access (how to probe and access test signals).

A conventional 2D test flow is proven and straightforward. It involves wafer probe, and, after packaging, final test. In the 3D world a disaggregated flow is much more likely. The individual dies are likely to come from different wafer fabs, and there are many questions about what should be tested when. Should dies be tested before stacking, and do they need KGD final-test quality, which includes at-speed testing and burnin? Should interconnects be re-tested every time a new die is added to the stack, or not until the entire stack is assembled? What will the final test include and who will do it?

At one extreme, it is possible to spend too much time and money on continual re-testing. At another extreme, not testing enough may result in a “penny wise and pound foolish” approach that results in low yields, Marinissen said. He noted that careful cost and yield modeling is needed to determine what steps the test flow should include for any given 3D-IC.

Pre-bond testing is done on the original or thinned-down wafer before stacking. It can be challenging for any die that will not be the bottom die in the stack. These “upper” dies receive all functional signals (power, clocks, control, data) Through Tsv interconnects, which are too small for current probe technology to handle. One workaround is for the IC designer to bring test signals out to larger, dedicated pre-bond test pads.

Unless yields for the individual dies are very high, pre-bond testing is probably cost effective. If individual dies are likely to have only a 90% yield, and four dies are placed in a 3D stack, the yield of the completed stacks will only average around 66%. It is less expensive to find a defective die at the pre-bond level than during post-bond testing.

Post-bond testing is done on a partial or complete stack. It assesses the quality of Tsv-based interconnects between stacked dies, and checks for additional defects that may have occurred due to stacking. Probe access is available only on the external I/Os of the stack, which are typically located on the bottom die only. Fortunately, the bottom die external I/Os lead to conventional wire-bond pads or flip-chip bonds that do not provide major test access challenges. However, the DFT architecture needs to propagate test data from the external I/Os up and down through the stack.

Post-packaging (or final) testing serves as the final check that determines the outgoing product quality to the customer. The designer should be able to test any die and Tsv-based interconnect layer in the stack. Test access will not require wafer probing, but will instead be based on sockets.

Ultimately, board-level interconnect test and board-level hardware/software debug will also be needed. For board test, the 3D-IC should be as transparent as possible to the board designer, and board testers should only Need to access the boundary scan interface of the stack.

3D-IC test challenges – Test content

All manufacturing defects that can occur in conventional 2D chips are relevant when these chips are in 3D stacks, including stuck-at, transition, delay, and IDDQ faults. However, the designer needs to provide new test content because there are new types of potential defects, particularly those due to added 3D processing steps and Tsv-based interconnects.

One 3D processing step that can cause new defects is wafer thinning. Tsv processing only allows limited heights and aspect ratios. If a Tsv has a 5ìm diameter and 1:10 aspect ratio, this would dictate a height of 50ìm. To expose the Tsvs, the wafer must be thinned to 50ìm from an original thickness of 750ìm. Wafer thinning may change transistor performance, degrade I-v characteristics, and cause yield losses.

Defects may also be due to thermal expansion and thermo-mechanical stress. Dies in the middle of a stack are especially prone to higher temperatures, and excessive heat can change the performance of devices or even lead to damage. Test itself can be a danger, as at-speed test may cause dies to heat up excessively. Designers must ensure adequate power to all dies in a stack, and avoid excessive noise or voltage drop.

Tsv-based interconnects may introduce defects during fabrication (liners, barriers, plating) or interconnect bonding (oxidation/ contamination, height variation, misalignment). Opens, shorts, and timing faults are possible. Imec and Cadence have worked together to develop an interconnect fault model and automatic test pattern generation (ATPG) capability to detect such defects.

3D-IC test challenges – Test access

Current probe technology cannot access Tsvs or micro-bumps. Tsvs typically have diameters around 5ìm and a 10ìm pitch, while microbumps may have diameters of 25 ìm and a 40ìm pitch. The minimum in-line pitch for today’s advanced wafer probe technology is well over 50ìm. Further, probes may leave scrub marks or cause pad damage. The industry is working to improve probe technology, but in the meantime, the IC designer should plan on adding dedicated pads in the DFT architecture.

Should pre-bond testing be done before or after wafer thinning, or perhaps both? Before wafer thinning (top below), handling is easier, but Tsvs are buried in thick substrate and access is available only on the front side. After wafer thinning (bottom), the wafer is placed on a temporary carrier wafer, and there is no front side access, so it’s necessary to probe on the back side of the thinned wafer. Probes can easily damage the thinned wafer.

A modular 3D-IC test architecture

In modular testing, chip modules such as embedded cores are tested as standalone units. Modular system-on-chip testing also enables heterogeneous circuit structures, “divide and conquer” ATPG, and test reuse. Modular testing of 3D-ICs can provide these capabilities as well as easy yield monitoring, first-order fault diagnosis, and the ability to flexibly optimize the 3D-IC test flow.

A 3D-IC DFT architecture, originally created at imec, was further developed and refined in co-operation with Cadence. The architecture has been proposed as a standard test-access architecture through the Ieee P1838 3D Test Working Group, which represents eDA, IP, Ate, and semiconductor vendors. “In the end, we feel it needs to be an industry solution,” Marinissen said.

In this DFT architecture, wrappers provide isolation and boundary-scan access for the internal testing of individual dies as well as interconnect between dies. The architecture supports pre-bond, mid-bond, and post-bond testing. It allows and complements any test structures that may be used on the individual dies, such as scan or BIST. “The architecture provides a way to get test data from any of the chips in the stack without overly Consuming a lot of test signals,” said Brion Keller, senior architect at Cadence.

The architecture supports both Ieee 1500 (embedded Core Test) and Ieee 1149.1 (JTAG) wrappers, but most of the initial work has focused on Ieee 1500. While the wrappers perform similar functions, there’s a difference. Ieee 1149.1 uses a single bit instruction/data interface, two or three control inputs, and a Test Access Port (TAP) controller. Ieee 1500 also provides a single bit serial interface but allows a scalable n-bit parallel data interface, along with six or seven control inputs.

The architecture also adds several 3D enhancements to test wrappers. One is called a “test elevator.” As previously stated, post bond test access is typically available only from the bottom die in the stack. A test elevator is needed to pass test data to and from dies above the bottom die, using dedicated Tsvs. A design with 1,000 functional Tsvs may only require 20 or so of these special test Tsvs.

Another wrapper enhancement allows “test turns” that return the test signals within a die, rather than passing signals on to the next die. Enhancements also provide additional probe pads for pre-bond test, and add registers To Provide a clean timing interface to output paths. A hierarchy of instruction control registers makes it possible to selectively test higher-level die.

A 3D-IC DFT architecture will only succeed if it can be implemented in eDA tools. For this reason, Cadence and imec have collaborated to develop a wrapper generation flow using the Cadence encounter RTL Compiler, and an innovative ATPG solution using interconnect fault modeling for Tsvs and micro-bumps in Cadence encounter Test. This interconnect ATPG is very efficient – a design with a million interconnects may require just tens of dedicated patterns. The solution uses what is called a “boundary skin” model that provides just enough information about the die to generate ATPG patterns.

Conclusion

3D-IC test is challenging, but it does not need to become a bottleneck. If design and manufacturing teams understand the challenges and work together, they can develop an appropriate test flow by doing cost modeling, adding test content for new 3D failure mechanisms, and using dedicated probe pads so long as probe technology cannot provide full access. A modular 3D-IC DFT architecture, such as the one described here, can alleviate many test challenges while providing controllability and observability for individual dies and Tsv interconnects. A standardized DFT architecture through Ieee P1838 will simplify a 3D-IC design, manufacturing and test flow supported by multiple industry providers.

To be continued in the November issue of 3D Packaging

www.cadence.com

www.gsaglobal.org

Samta Bansal leads 3D-IC efforts among others for Applied Silicon Realization at Cadence Design Systems, Inc.

She has more than 12 years of experience working with semiconductor leaders including both 2D and 3D-IC design space. Prior to Cadence, Samta worked at Synopsys looking into the front end technologies. With hands on experience on front end for 8 years and moving to Back end, Samta has a very good understanding of the evolution and challenges the industry has been going in terms of design requirements and is very passion ate in driving this shift of the industry from 2D to 3D-IC within Cadence and working with the ecosystem partners. Samta has Masters in Physics, Bachelors in eee from Birla Institute of Technology and Science(BITS), Pilani and MBA from Santa Clara University.

Herb Reiter, Chair of the GSA’s 3D-IC Working Group and consultant for the GSA since 2008.

He founded eda2asic Consulting in the spring of 2002 to increase cooperation between eDA suppliers and semiconductor vendors. In this role Herb introduced many eDA tools, flows and methodologies to reduce IC design time for the semiconductor vendors and to lower power dissipation and unit cost for their products. Previously Herb worked for 5 years in business development roles at Barcelona Design, Synopsys and viewlogic. The PrimeTime sign-off wave and the TSMC reference flow # 1 are highlights of Herb’s accomplishments at Synopsys. From 1980 to 1997 Herb worked in both business and technical roles at vLSI Technology and national Semiconductor to market ASICs and ASSPs. Herb earned an MBA at San Jose State University and Master Degrees in Business and in electrical engineering at the University and at the Technical College in Linz/Austria, respectively.
VIEW ALL ARTICLES
Message
SEND